Chui, Chi On
Chi On Chui, Associate Professor
Northrop Grumman Teaching Awards, 2011
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) Best Student Paper Award, 2010
IEEE Electron Devices Society Early Career Award, 2009
Research Group: Nanostructure Devices and Technology Laboratory
Office: 6730B Boelter Hall, Phone: 310.267.4786, Email
Chi On Chui received the B.Eng. degree in Electronic Engineering (with highest honors) from the Hong Kong University of Science and Technology (HKUST) in 1999, and the M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 2001 and 2004, respectively. He joined the Intel Corporation as a Senior Device Engineer in 2004 to research and evaluate post-silicon transistor technologies for high performance logic applications. During his tenure with Intel, he served as a Researcher-in-Residence at the University of California, Berkeley and at Stanford University. From 2005-2006, he was also appointed Consulting Assistant Professor of Electrical Engineering at Stanford University. In January 2007, he joined the faculty of the University of California, Los Angeles (UCLA) as an Assistant Professor of Electrical Engineering. Since 2009, he has been an elected Member of the UCLA's California NanoSystems Institute (CNSI).
Prof. Chui is an early advocate of the use of high mobility semiconductor in MOSFETs and seminally demonstrated the incorporation of nanoscale high-permittivity gate dielectrics for germanium MOS device applications. He has received several awards including HKUST's Academic Achievement Award in 1999, the Intel Foundation Ph.D. Fellowship in 2003, the Microsoft Academic Research Grant in 2003, the Okawa Foundation Award in 2007, and the IEEE Electron Devices Society Early Career Award in 2009. In addition, his works have won the best paper awards at the 60th IEEE Device Research Conference (DRC) in 2002, the 13th Workshop on Dielectrics in Microelectronics (WoDiM) in 2004, and the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) in 2010. He has delivered one keynote speech and numerous invited talks. He is a named inventor on five issued patents, and few other pending patents in semiconductor device technology. He has authored or co-authored more than 85 peer-reviewed archival journal and conference papers (including two review papers and 23 invited papers) and five book chapters.
Dr. Chui is a Senior Member of the IEEE and a past member of the Materials Research Society (MRS). He has served on the International Advisory Committee of the International Symposium on Advanced Fluid Information and Transdisciplinary Fluid Integration (AFI/TFI) and the IEEE International Conference on Computer, Control & Communication (IEEE-IC4). He also served on the Technical Program Committee of the IEEE International Electron Devices Meeting (IEDM) and IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
Prof. Chui's current research focuses on developing top-down and bottom-up nanotechnology for nanoarchitectonics, nanotheranostics, and nanoelectronics.
Awards and Recognitions
- 2011 Northrop Grumman Teaching Awards
- 2011 CAFA Robert T. Poe Faculty Development Award
2010 The 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) Best Student Paper Award
2009 IEEE Electron Devices Society Early Career Award (1st Recipient)
2007 Okawa Foundation Award
2004 The 13th Workshop on Dielectrics in Microelectronics (WoDIM 2004) Best Paper Award
2002 IEEE 60th Device Research Conference (DRC) Best Paper Award
1999 Hong Kong University of Science and Technology (HKUST) Academic Achievement Medal